The present invention relates to a clock pulse generator for use in digital television receivers, video tape recorders and the like, and, particularly, relates to a clock pulse generator for use in horizontal synchronizing signal generation circuits and signal processing circuits.
FIGS. 1A and 1B are block diagrams respectively showing conventional clock pulse generators.
In FIGS. 1A and 1B, the reference numeral 1 designates a video signal input terminal, 2 a line lock clock pulse generation circuit, 3 a line lock clock pulse signal (generated in synchronism with a horizontal synchronizing signal contained in an input video signal), 4 a burst lock clock pulse generation circuit, 5 a burst lock clock pulse signal (generated in synchronism with a color burst signal contained in the video signal), 9 a synchronizing signal generation circuit, 10 a signal processing circuit, 11 a synchronizing signal output terminal and 12 a video signal output terminal.
First, the circuit shown in FIG. 1A is described hereunder.
The burst lock clock pulse generation circuit 4 generates a stable burst lock clock pulse signal 5 by use of a quartz oscillator (not shown) in synchronism with a color burst signal contained in a video signal entering at the video signal input terminal 1. The input video signal is a signal according to a standard television broadcasting system (hereinafter called "standard signal"). In an NTSC system, the frequency (fsc) of the color burst signal contained in the standard signal and the frequency (f.sub.H) of the horizontal synchronizing signal have the following relation. ##EQU1##
Next, the synchronizing signal generation circuit 9 receives the burst lock clock pulse signal 5 supplied from the burst lock clock pulse generation circuit 4 and generates a synchronizing signal by using the relation expressed by the equation (1).
The signal processing circuit 10 receives both the video signal supplied through the video signal input terminal 1 and the burst lock clock pulse signal 5 supplied from the burst lock clock pulse generation circuit 4 and performs signal processing on the video signal by using the relation expressed by the equation (1) to thereby improve the picture quality of the video signal. As an example of such a conventional circuit for improving the picture quality of the video signal, for example, there is that disclosed in JP-A-62-268274 specification.
That disclosed in the above JP-A-62-268274 specification relates to a horizontal synchronizing regeneration circuit having a horizontal synchronizing oscillation frequency fine tuning delay circuit arranged in front of an oscillation circuit. The delay circuit freely delays measured clock pulses generated by a voltage-controlled oscillator within a range of one clock pulse interval to make it possible to fine tune the frequency of the measured clock pulses. By counting down the fine-tuned measured clock pulses in the following oscillation circuit, a regenerative horizontal synchronizing signal phase-locked with the oscillation frequency is obtained.
In the following, the circuit shown in FIG. 1B is described.
The line lock clock pulse generation circuit 2 generates a line lock clock pulse signal 3 in synchronism with a horizontal synchronizing signal contained in a video signal supplied through the video signal input terminal 1.
Next, the synchronizing signal generation circuit 9 receives the line lock clock pulse signal 3 supplied from the line lock clock pulse generation circuit 2 and generates a synchronizing signal.
The signal processing circuit 10 receives both the video signal supplied through the video signal input terminal 1 and the line lock clock pulse signal 3 supplied from by the line lock clock pulse generation circuit 2 and performs signal processing on the video signal.
As an example of such a conventional circuit as shown in FIG. 1B, for example, there is that disclosed in JP-A-63-193783 specification.
That disclosed in the above JP-A-63-193783 specification relates to an n-fold speed scanning television receiver having a double speed horizontal synchronizing generation circuit and a double speed horizontal deflection circuit which are arranged in one phase lock circuit. In this conventional circuit, the input video signal is subjected to double speed conversion and double density scanning by using a digital circuit. Accordingly, the conventional circuit is suitable for the case where input signals of two systems (for example, a standard signal and a double speed signal) exist.
In recent years, development of television receivers has been activated to put into practice IDTV (improved definition television receivers) in which picture quality is improved by replacing the conventional analog signal processing video circuit by a digital signal processing video circuit.
A conventional clock generation and synchronizing deflection circuit used in the IDTV is shown in FIG. 2. In FIG. 2, the reference numeral 201 designates an input terminal, 202 a phase comparator (PD), 203 a low-pass filter (LPF), 204 a voltage-controlled oscillator (VCO), 205 a 1/910 frequency divider, 206 a horizontal output circuit, 207 a flyback transformer (FBT), and 208 and 209 1/2 frequency dividers.
The horizontal synchronizing signal supplied to the input terminal 201 is compared with the output of the 1/2 frequency divider 208 supplied to the other input signal thereof inputted to the phase comparator 202 the result of comparison being put out as a signal corresponding to the phase difference between the two input signals. The output signal of the phase comparator 202 is filtered by the low-pass filter 203 so as to attain a predetermined response characteristic and then the output of the low-pass filter is supplied to the voltage-controlled oscillator 204. The voltage-controlled oscillator 204 generates a signal having an oscillation frequency corresponding to the output of the low-pass filter 203. The frequency of the output of the voltage-controlled oscillator 204 is divided into 1/910 by the 1/910 frequency divider 205 so as to produce a double speed horizontal synchronizing signal 205-output. At the same time, the horizontal synchronizing signal 205-output is supplied to the horizontal output circuit 206 to perform horizontal scanning. A deflection york drive signal for the horizontal scanning is amplified by the flyback transformer 207. The frequency of a flyback pulse signal generated in the secondary side of the flyback transformer is divided by the 1/2 frequency divider 208 and then supplied to the phase comparator 202. The circuits 202 to 208 constitute a feed-back control circuit for performing phase locking between the input signal supplied to the input terminal 201 and the output of the 1/2 frequency divider 208.
In order to perform digital signal processing, in addition to the 205-output which is equal in frequency to the output of the horizontal output circuit 206, the 209-output which is equal in period to the horizontal period of the input signal is obtained by dividing the frequency of output of the 1/910 frequency divider 205 into 1/2 by the 1/2 divider 209.
As an example of such a conventional technique, for example, there is that disclosed in JP-A-64-29174 specification.
That disclosed in the above JP-A-64-29174 specification relates to a clock pulse generation circuit in which, in FIG. 2, a horizontal synchronizing signal of a television receiver is supplied to a first phase lock circuit so as to produce a double speed horizontal pulse signal, and the double speed horizontal pulse signal is supplied to a second phase lock circuit so as to produce a desired clock pulse signal.
However, the respective conventional techniques have the following disadvantages.
The circuit shown in FIG. 1A has an advantage in that not only a very stable synchronizing signal can be generated but picture quality in the video signal can be improved, in the case where the video signal supplied to the video input terminal 1 is a standard signal.
However, the circuit has no consideration upon a signal out of standard (hereinafter called "non-standard signal") which is not strictly in accord with the standard with respect to the standard television broadcasting system, such as a video signal reproduced by a VTR (video tape recorder), that is to say, a signal which does not satisfy the relation expressed by the equation (1). Accordingly, in the case where such a non standard signal is supplied, there arises a problem in that not only the picture quality cannot be improved but the stability of phase lock cannot be attained.
On the other hand, the circuit shown in FIG. 1B has an advantage in that synchronization can be made sufficiently even in the case where a non-standard signal is supplied. Accordingly, the circuit can cope with video signals supplied from various appliances different in the pull-in range. Further, the picture quality can be improved within a range in which the relation is not used, because the relation expressed by the equation (1)is not kept as described above when a non-standard signal is supplied.
However, in the case where a standard signal satisfying the relation (1)is supplied, the picture quality cannot be improved sufficiently because the Q value of an oscillator (not shown) contained in the line lock clock pulse generation circuit 2 in the circuit of FIG. 1B is lower than that of a quartz oscillator contained in the burst lock clock generation circuit 4 in the circuit of FIG. 1A, and, accordingly, because the stability of the generated clock pulse signal in the circuit of FIG. 1B is lower than that in the circuit of FIG. 1A.
In the conventional technique as shown in FIG. 2, the Q value of the voltage-controlled oscillator 204 is generally established to be so low to answer video signals of various appliances in which the horizontal frequency is not exactly controlled. Accordingly, the clock pulse signal generated by the circuit shown in FIG. 2 is poor in stability. Accordingly, the jitter of the clock pulse signal is so large that the arrangement of picture elements with respect to lines and fields cannot be grasped exactly. Consequently, in the conventional technique shown in FIG. 2, the effect for improvement of picture quality is very small.